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M93S66, M93S56 M93S46
4Kbit, 2Kbit and 1Kbit (16-bit wide) MICROWIRE Serial Access EEPROM with Block Protection
FEATURES SUMMARY

Industry Standard MICROWIRE Bus Single Supply Voltage: - 4.5 to 5.5V for M93Sx6 - 2.5 to 5.5V for M93Sx6-W - 1.8 to 5.5V for M93Sx6-R Single Organization: by Word (x16) Programming Instructions that work on: Word or Entire Memory Self-timed Programming Cycle with AutoErase User Defined Write Protected Area Page Write Mode (4 words) Ready/Busy Signal During Programming Speed: - 1MHz Clock Rate, 10ms Write Time (Current product, identified by process identification letter F or M) - 2MHz Clock Rate, 5ms Write Time (New Product, identified by process identification letter W or G) Sequential Read Operation Enhanced ESD/Latch-Up Behavior More than 1 Million Erase/Write Cycles More than 40 Year Data Retention
Figure 1. Packages
8 1
PDIP8 (BN)
8 1
SO8 (MN) 150 mil width
TSSOP8 (DS) 3x3mm body size
TSSOP8 (DW) 169 mil width
April 2004
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M93S66, M93S56, M93S46
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. DIP, SO and TSSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 POWER-ON DATA PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2. Instruction Set for the M93S46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Instruction Set for the M93S66, M93S56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. READ, WRITE, WEN and WDS Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write Enable and Write Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 5. PAWRITE and WRAL Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 6. PREAD, PRWRITE and PREN Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 7. PRCLEAR and PRDS Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 WRITE PROTECTION AND THE PROTECTION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Protection Register Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Protection Register Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Protection Register Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Protection Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Protection Register Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 COMMON I/O OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8. Write Sequence with One Clock Glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 CLOCK PULSE COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5. Table 6. Table 7. Table 8. Table 9.
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Operating Conditions (M93Sx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Operating Conditions (M93Sx6-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Operating Conditions (M93Sx6-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AC Measurement Conditions (M93Sx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AC Measurement Conditions (M93Sx6-W and M93Sx6-R). . . . . . . . . . . . . . . . . . . . . . . 17
M93S66, M93S56, M93S46
Figure 9. AC Testing Input Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 10. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 11. DC Characteristics (M93Sx6, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 12. DC Characteristics (M93Sx6, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 13. DC Characteristics (M93Sx6-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 14. DC Characteristics (M93Sx6-W, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 15. DC Characteristics (M93Sx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 16. AC Characteristics (M93Sx6, Device Grade 6 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 17. AC Characteristics (M93Sx6-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 18. AC Characteristics (M93Sx6-W, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 19. AC Characteristics (M93Sx6-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 10.Synchronous Timing (Start and Op-Code Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 11.Synchronous Timing (Read or Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 12.Synchronous Timing (Read or Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 13.PDIP8 - 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 28 Table 20. PDIP8 - 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . . 28 Figure 14.SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 29 Table 21. SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data 29 Figure 15.TSSOP8 3x3mm - 8 lead Thin Shrink Small Outline, 3x3mm body size, Package Outline 30 Table 22. TSSOP8 3x3mm - 8 lead Thin Shrink Small Outline, 3x3mm body size, Mechanical Data 30 Figure 16.TSSOP8 - 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 31 Table 23. TSSOP8 - 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 31 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 24. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 25. How to Identify Current and New Products by the Process Identification Letter . . . . . . . 32 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 26. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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M93S66, M93S56, M93S46
SUMMARY DESCRIPTION
This specification covers a range of 4K, 2K, 1K bit serial Electrically Erasable Programmable Memory (EEPROM) products (respectively for M93S66, M93S56, M93S46). In this text, these products are collectively referred to as M93Sx6. Figure 2. Logic Diagram and instructions used to set the memory protection. These are summarized in Table 2. and Table 3.). A Read Data from Memory (READ) instruction loads the address of the first word to be read into an internal address pointer. The data contained at this address is then clocked out serially. The address pointer is automatically incremented after the data is output and, if the Chip Select Input (S) is held High, the M93Sx6 can output a sequential stream of data words. In this way, the memory can be read as a data stream from 16 to 4096 bits (for the M93S66), or continuously as the address counter automatically rolls over to 00h when the highest address is reached. Within the time required by a programming cycle (tW), up to 4 words may be written with help of the Page Write instruction. the whole memory may also be erased, or set to a predetermined pattern, by using the Write All instruction. Within the memory, a user defined area may be protected against further Write instructions. The size of this area is defined by the content of a Protection Register, located outside of the memory array. As a final protection step, data may be permanently protected by programming a One Time Programming bit (OTP bit) which locks the Protection Register content. Programming is internally self-timed (the external clock signal on Serial Clock (C) may be stopped or left running after the start of a Write cycle) and does not require an erase cycle prior to the Write instruction. The Write instruction writes 16 bits at a time into one of the word locations of the M93Sx6, the Page Write instruction writes up to 4 words of 16 bits to sequential locations, assuming in both cases that all addresses are outside the Write Protected area. After the start of the programming cycle, a Busy/Ready signal is available on Serial Data Output (Q) when Chip Select Input (S) is driven High. Figure 3. DIP, SO and TSSOP Connections
VCC
D C S PRE W M93Sx6 Q
VSS
AI02020
Table 1. Signal Names
S D Q C PRE W VCC VSS Chip Select Input Serial Data Input Serial Data Output Serial Clock Protection Register Enable Write Enable Supply Voltage Ground
M93Sx6 S C D Q 1 2 3 4 8 7 6 5
AI02021
The M93Sx6 is accessed through a serial input (D) and output (Q) using the MICROWIRE bus protocol. The memory is divided into 256, 128, 64 x16 bit words (respectively for M93S66, M93S56, M93S46). The M93Sx6 is accessed by a set of instructions which includes Read, Write, Page Write, Write All
VCC PRE W VSS
Note: See PACKAGE MECHANICAL section for package dimensions, and how to identify pin-1.
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An internal Power-on Data Protection mechanism in the M93Sx6 inhibits the device when the supply is too low.
INSTRUCTIONS
The instruction set of the M93Sx6 devices contains seven instructions, as summarized in Table 2. to Table 3.. Each instruction consists of the following parts, as shown in Figure 4.: Each instruction is preceded by a rising edge on Chip Select Input (S) with Serial Clock (C) being held Low. A start bit, which is the first `1' read on Serial Data Input (D) during the rising edge of Serial Clock (C). Two op-code bits, read on Serial Data Input (D) during the rising edge of Serial Clock (C). (Some instructions also use the first two bits of the address to define the op-code). The address bits of the byte or word that is to be accessed. For the M93S46, the address is made up of 6 bits (see Table 2.). For the M93S56 and M93S66, the address is made up of 8 bits (see Table 3.). The M93Sx6 devices are fabricated in CMOS technology and are therefore able to run as slow as 0 Hz (static input signals) or as fast as the maximum ratings specified in Table 16. to Table 19..
POWER-ON DATA PROTECTION
To prevent data corruption and inadvertent write operations during power-up, a Power-On Reset (POR) circuit resets all internal programming circuitry, and sets the device in the Write Disable mode. - At Power-up and Power-down, the device must not be selected (that is, Chip Select Input (S) must be driven Low) until the supply voltage reaches the operating value VCC specified in Table 5. to Table 6.. - When VCC reaches its valid level, the device is properly reset (in the Write Disable mode) and is ready to decode and execute incoming instructions. For the M93Sx6 devices (5V range) the POR threshold voltage is around 3V. For the M93Sx6W (3V range) and M93Sx6-R (2V range) the POR threshold voltage is around 1.5V.
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M93S66, M93S56, M93S46
Table 2. Instruction Set for the M93S46
Instruction Description Read Data from Memory Write Data to Memory W PRE Start bit 1 OpCode 10 Address1 Data Required Clock Cycles Additional Comments
READ
X
0
A5-A0
Q15-Q0 Write is executed if the address is not inside the Protected area
WRITE
1
0
1
01
A5-A0
D15-D0
25
PAWRITE
Page Write to Memory Write All Memory with same Data Write Enable Write Disable Protection Register Read
1
0
1
11
A5-A0
Nx D15-D0
Write is executed if all the N addresses 9 + N x 16 are not inside the Protected area Write all data if the Protection Register is cleared
WRAL
1
0
1
00
01 XXXX
D15-D0
25
WEN WDS
1 X
0 0
1 1
00 00
11 XXXX 00 XXXX Q5-Q0 + Flag
9 9 Data Output = Protection Register content + Protection Flag bit 9 Data above specified address A5-A0 are protected Protect Flag is also cleared (cleared Flag = 1)
PRREAD
X
1
1
10
XXXXXX
PRWRITE
Protection Register Write Protection Register Clear Protection Register Enable Protection Register Disable
1
1
1
01
A5-A0
PRCLEAR
1
1
1
11
111111
9
PREN
1
1
1
00
11XXXX
9
PRDS
1
1
1
00
000000
9
OTP bit is set permanently
Note: 1. X = Don't Care bit.
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Table 3. Instruction Set for the M93S66, M93S56
Instruction Description Read Data from Memory Write Data to Memory W PRE Start bit 1 OpCode 10 Address1,2 Data Required Clock Cycles Additional Comments
READ
X
0
A7-A0
Q15-Q0 Write is executed if the address is not inside the Protected area
WRITE
1
0
1
01
A7-A0
D15-D0
27
PAWRITE
Page Write to Memory
1
0
1
11
A7-A0
Write is executed if all the N Nx 11 + N x 16 addresses are not D15-D0 inside the Protected area Write all data if the Protection Register is cleared
WRAL
Write All Memory with same Data Write Enable Write Disable Protection Register Read
1
0
1
00
01XXXXXX
D15-D0
27
WEN WDS
1 X
0 0
1 1
00 00
11XXXXXX 00XXXXXX Q7-Q0 + Flag
11 11 Data Output = Protection Register content + Protection Flag bit Data above specified address A7-A0 are protected Protect Flag is also cleared (cleared Flag = 1)
PRREAD
X
1
1
10
XXXXXXXX
PRWRITE
Protection Register Write
1
1
1
01
A7-A0
11
PRCLEAR
Protection Register Clear Protection Register Enable Protection Register Disable
1
1
1
11
11111111
11
PREN
1
1
1
00
11XXXXXX
11
PRDS
1
1
1
00
00000000
11
OTP bit is set permanently
Note: 1. X = Don't Care bit. 2. Address bit A7 is not decoded by the M93S56.
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Figure 4. READ, WRITE, WEN and WDS Sequences
READ PRE
S
D
1 1 0 An
A0
Q ADDR OP CODE
Qn DATA OUT
Q0
WRITE
PRE
W
S CHECK STATUS D 1 0 1 An A0 Dn D0
Q ADDR OP CODE DATA IN BUSY READY
WRITE ENABLE
PRE
WRITE DISABLE
PRE
W
S
S
D
1 0 0 0 0 Xn X0
D
1 0 0 1 1 Xn X0
OP CODE
OP CODE
AI00889D
Note: For the meanings of An, Xn, Qn and Dn, see Table 2. and Table 3..
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Read The Read Data from Memory (READ) instruction outputs serial data on Serial Data Output (Q). When the instruction is received, the op-code and address are decoded, and the data from the memory is transferred to an output shift register. A dummy 0 bit is output first, followed by the 16-bit word, with the most significant bit first. Output data changes are triggered by the rising edge of Serial Clock (C). The M93Sx6 automatically increments the internal address register and clocks out the next byte (or word) as long as the Chip Select Input (S) is held High. In this case, the dummy 0 bit is not output between bytes (or words) and a continuous stream of data can be read. Write Enable and Write Disable The Write Enable (WEN) instruction enables the future execution of write instructions, and the Write Disable (WDS) instruction disables it. When power is first applied, the M93Sx6 initializes itself so that write instructions are disabled. After an Write Enable (WEN) instruction has been executed, writing remains enabled until an Write Disable (WDS) instruction is executed, or until V CC falls below the power-on reset threshold voltage. To protect the memory contents from accidental corruption, it is advisable to issue the Write Disable (WDS) instruction after every write cycle. The Read Data from Memory (READ) instruction is not affected by the Write Enable (WEN) or Write Disable (WDS) instructions. Write The Write Data to Memory (WRITE) instruction is composed of the Start bit plus the op-code followed by the address and the 16 data bits to be written. Write Enable (W) must be held High before and during the instruction. Input address and data, on Serial Data Input (D) are sampled on the rising edge of Serial Clock (C). After the last data bit has been sampled, the Chip Select Input (S) must be taken Low before the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought Low before or after this specific time frame, the self-timed programming cycle will not be started, and the addressed location will not be programmed. While the M93Sx6 is performing a write cycle, but after a delay (tSLSH) before the status information becomes available, Chip Select Input (S) can be driven High to monitor the status of the write cycle: Serial Data Output (Q) is driven Low while the M93Sx6 is still busy, and High when the cycle is complete, and the M93Sx6 is ready to receive a new instruction. The M93Sx6 ignores any data on the bus while it is busy on a write cycle. Once the M93Sx6 is Ready, Serial Data Output (Q) is driven High, and remains in this state until a new start bit is decoded or the Chip Select Input (S) is brought Low. Programming is internally self-timed, so the external Serial Clock (C) may be disconnected or left running after the start of a write cycle.
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Figure 5. PAWRITE and WRAL Sequence
PAGE WRITE PRE
W
S CHECK STATUS D 1 1 1 An A0 Dn D0
Q ADDR OP CODE DATA IN BUSY READY
WRITE ALL
PRE
W
S CHECK STATUS D 1 0 0 0 1 Xn X0 Dn D0
Q ADDR OP CODE
AI00890C
DATA IN
BUSY
READY
Note: For the meanings of An, Xn and Dn, please see Table 2. and Table 3..
Page Write A Page Write to Memory (PAWRITE) instruction contains the first address to be written, followed by up to 4 data words. After the receipt of each data word, bits A1-A0 of the internal address register are incremented, the high order bits remaining unchanged (A7-A2 for M93S66, M93S56; A5-A2 for M93S46). Users must take care, in the software, to ensure that the last word address has the same upper order address bits as the initial address transmitted to avoid address roll-over.
The Page Write to Memory (PAWRITE) instruction will not be executed if any of the 4 words addresses the protected area. Write Enable (W) must be held High before and during the instruction. Input address and data, on Serial Data Input (D) are sampled on the rising edge of Serial Clock (C). After the last data bit has been sampled, the Chip Select Input (S) must be taken Low before the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought Low before or after this specific time frame, the self-timed programming cycle will not
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be started, and the addressed location will not be programmed. While the M93Sx6 is performing a write cycle, but after a delay (tSLSH) before the status information becomes available, Chip Select Input (S) can be driven High to monitor the status of the write cycle: Serial Data Output (Q) is driven Low while the M93Sx6 is still busy, and High when the cycle is complete, and the M93Sx6 is ready to receive a new instruction. The M93Sx6 ignores any data on the bus while it is busy on a write cycle. Once the M93Sx6 is Ready, Serial Data Output (Q) is driven High, and remains in this state until a new start bit is decoded or the Chip Select Input (S) is brought Low. Programming is internally self-timed, so the external Serial Clock (C) may be disconnected or left running after the start of a write cycle. Write All The Write All Memory with same Data (WRAL) instruction is valid only after the Protection Register has been cleared by executing a Protection Register Clear (PRCLEAR) instruction. The Write All Memory with same Data (WRAL) instruction simultaneously writes the whole memory with the same data word given in the instruction. Write Enable (W) must be held High before and during the instruction. Input address and data, on Serial Data Input (D) are sampled on the rising edge of Serial Clock (C). After the last data bit has been sampled, the Chip Select Input (S) must be taken Low before the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought Low before or after this specific time frame, the self-timed programming cycle will not be started, and the addressed location will not be programmed. While the M93Sx6 is performing a write cycle, but after a delay (tSLSH) before the status information becomes available, Chip Select Input (S) can be driven High to monitor the status of the write cycle: Serial Data Output (Q) is driven Low while the M93Sx6 is still busy, and High when the cycle is complete, and the M93Sx6 is ready to receive a new instruction. The M93Sx6 ignores any data on the bus while it is busy on a write cycle. Once the M93Sx6 is Ready, Serial Data Output (Q) is driven High, and remains in this state until a new start bit is decoded or the Chip Select Input (S) is brought Low. Programming is internally self-timed, so the external Serial Clock (C) may be disconnected or left running after the start of a write cycle.
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M93S66, M93S56, M93S46
Figure 6. PREAD, PRWRITE and PREN Sequences
Protect Register READ
PRE
S
D
1 1 0 Xn
X0
Q ADDR OP CODE
An
A0 F DATA OUT F = Protect Flag
Protect Register WRITE
PRE
W
S CHECK STATUS D 1 0 1 An A0
Q ADDR OP CODE BUSY READY
Protect Register ENABLE
PRE
W
S
D
1 0 0 1 1 Xn X0
OP CODE
Note: For the meanings of An, Xn and Dn, please see Table 2. and Table 3..
AI00891D
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Figure 7. PRCLEAR and PRDS Sequences
Protect Register CLEAR PRE
W
S CHECK STATUS D 111 111
Q ADDR OP CODE BUSY READY
Protect Register DISABLE
PRE
W
S CHECK STATUS D 100 000
Q ADDR OP CODE
AI00892C
BUSY
READY
Note: For the meanings of An, Xn and Dn, please see Table 2. and Table 3..
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WRITE PROTECTION AND THE PROTECTION REGISTER
The Protection Register on the M93Sx6 is used to adjust the amount of memory that is to be write protected. The write protected area extends from the address given in the Protection Register, up to the top address in the M93Sx6 device. Two flag bits are used to indicate the Protection Register status: - Protection Flag: this is used to enable/disable protection of the write-protected area of the M93Sx6 memory - OTP bit: when set, this disables access to the Protection Register, and thus prevents any further modifications to the value in the Protection Register. The lower-bound memory address is written to the Protection Register using the Protection Register Write (PRWRITE) instruction. It can be read using the Protection Register Read (PRREAD) instruction. The Protection Register Enable (PREN) instruction must be executed before any PRCLEAR, PRWRITE or PRDS instruction, and with appropriate levels applied to the Protection Enable (PRE) and Write Enable (W) signals. Write-access to the Protection Register is achieved by executing the following sequence: - Execute the Write Enable (WEN) instruction - Execute the Protection Register Enable (PREN) instruction - Execute one PRWRITE, PRCLEAR or PRDS instructions, to set a new boundary address in the Protection Register, to clear the protection address (to all 1s), or permanently to freeze the value held in the Protection Register. Protection Register Read The Protection Register Read (PRREAD) instruction outputs, on Serial Data Output (Q), the content of the Protection Register, followed by the Protection Flag bit. The Protection Enable (PRE) signal must be driven High before and during the instruction. As with the Read Data from Memory (READ) instruction, a dummy 0 bit is output first. Since it is not possible to distinguish between the Protection Register being cleared (all 1s) or having been written with all 1s, the user must check the Protection Flag status (and not the Protection Register content) to ascertain the setting of the memory protection. Protection Register Enable The Protection Register Enable (PREN) instruction is used to authorize the use of instructions that modify the Protection Register (PRWRITE, PRCLEAR, PRDS). The Protection Register Enable (PREN) instruction does not modify the Protection Flag bit value. Note: A Write Enable (WEN) instruction must be executed before the Protection Register Enable (PREN) instruction. Both the Protection Enable (PRE) and Write Enable (W) signals must be driven High during the instruction execution. Protection Register Clear The Protection Register Clear (PRCLEAR) instruction clears the address stored in the Protection Register to all 1s, so that none of the memory is write-protected by the Protection Register. However, it should be noted that all the memory remains protected, in the normal way, using the Write Enable (WEN) and Write Disable (WDS) instructions. The Protection Register Clear (PRCLEAR) instruction clears the Protection Flag to 1. Both the Protection Enable (PRE) and Write Enable (W) signals must be driven High during the instruction execution. Note: A Protection Register Enable (PREN) instruction must immediately precede the Protection Register Clear (PRCLEAR) instruction. Protection Register Write The Protection Register Write (PRWRITE) instruction is used to write an address into the Protection Register. This is the address of the first word to be protected. After the Protection Register Write (PRWRITE) instruction has been executed, all memory locations equal to and above the specified address are protected from writing. The Protection Flag bit is set to 0, and can be read with Protection Register Read (PRREAD) instruction. Both the Protection Enable (PRE) and Write Enable (W) signals must be driven High during the instruction execution. Note: A Protection Register Enable (PREN) instruction must immediately precede the Protection Register Write (PRWRITE) instruction, but it is not necessary to execute first a Protection Register Clear (PRCLEAR). Protection Register Disable The Protection Register Disable (PRDS) instruction sets the One Time Programmable (OTP) bit. This instruction is a ONE TIME ONLY instruction which latches the Protection Register content, this content is therefore unalterable in the future. Both the Protection Enable (PRE) and Write Enable (W) signals must be driven High during the instruction execution. The OTP bit cannot be directly read, it can be checked by reading the content of the Protection Register, using the Protection Register Read (PRREAD) instruction, then by writing this same value back into the Protection Register, us-
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M93S66, M93S56, M93S46
ing the Protection Register Write (PRWRITE) instruction. When the OTP bit is set, the Ready/Busy status cannot appear on Serial Data Output (Q). When the OTP bit is not set, the Busy status appears on Serial Data Output (Q). Note: A Protection Register Enable (PREN) instruction must immediately precede the Protection Register Disable (PRDS) instruction.
COMMON I/O OPERATION
Serial Data Output (Q) and Serial Data Input (D) can be connected together, through a current limiting resistor, to form a common, single-wire data bus. Some precautions must be taken when operating the memory in this way, mostly to prevent a short circuit current from flowing when the last address bit (A0) clashes with the first data bit on Serial Data Output (Q). Please see the application note AN394 for details.
Figure 8. Write Sequence with One Clock Glitch
S
C
D
An START "0" WRITE "1"
An-1 Glitch
An-2 D0
ADDRESS AND DATA ARE SHIFTED BY ONE BIT
AI01395
CLOCK PULSE COUNTER
In a noisy environment, the number of pulses received on Serial Clock (C) may be greater than the number delivered by the Bus Master (the microcontroller). This can lead to a misalignment of the instruction of one or more bits (as shown in Figure 8.) and may lead to the writing of erroneous data at an erroneous address. To combat this problem, the M93Sx6 has an onchip counter that counts the clock pulses from the start bit until the falling edge of the Chip Select Input (S). If the number of clock pulses received is not the number expected, the WRITE, PAWRITE, WRALL, PRWRITE or PRCLEAR instruction is
aborted, and the contents of the memory are not modified. The number of clock cycles expected for each instruction, and for each member of the M93Sx6 family, are summarized in Table 2. to Table 3.. For example, a Write Data to Memory (WRITE) instruction on the M93S56 (or M93S66) expects 27 clock cycles from the start bit to the falling edge of Chip Select Input (S). That is: 1 Start bit + 2 Op-code bits + 8 Address bits + 16 Data bits
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M93S66, M93S56, M93S46
MAXIMUM RATING
Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 4. Absolute Maximum Ratings
Symbol TSTG TLEAD VOUT VIN VCC VESD Storage Temperature Lead Temperature during Soldering Output range (Q = VOH or Hi-Z) Input range Supply Voltage Electrostatic Discharge Voltage (Human Body model) 2 Parameter Min. -65 Max. 150 Unit C C V V V V
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
See note 1 -0.50 -0.50 -0.50 -4000
(R)
VCC+0.5 VCC+1 6.5 4000
Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 )
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DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the MeasureTable 5. Operating Conditions (M93Sx6)
Symbol VCC TA Ambient Operating Temperature (Device Grade 3) -40 125 C Supply Voltage Ambient Operating Temperature (Device Grade 6) Parameter Min. 4.5 -40 Max. 5.5 85 Unit V C
ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Table 6. Operating Conditions (M93Sx6-W)
Symbol VCC TA Supply Voltage Ambient Operating Temperature (Device Grade 6) Parameter Min. 2.5 -40 Max. 5.5 85 Unit V C
Table 7. Operating Conditions (M93Sx6-R)
Symbol VCC TA Supply Voltage Ambient Operating Temperature (Device Grade 6) Parameter Min. 1.8 -40 Max. 5.5 85 Unit V C
Table 8. AC Measurement Conditions (M93Sx6)
Symbol CL Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages
Note: Output Hi-Z is defined as the point where data out is no longer driven.
Parameter
Min. 100
Max.
Unit pF
50 0.4 V to 2.4 V 1.0 V and 2.0 V 0.8 V and 2.0 V
ns V V V
Table 9. AC Measurement Conditions (M93Sx6-W and M93Sx6-R)
Symbol CL Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages
Note: Output Hi-Z is defined as the point where data out is no longer driven.
Parameter
Min. 100
Max.
Unit pF
50 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC 0.3VCC to 0.7VCC
ns V V V
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Figure 9. AC Testing Input Output Waveforms
M93SXX 2.4V 2V 1V 0.4V INPUT OUTPUT 2.0V 0.8V
M93SXX-W & M93SXX-R 0.8VCC 0.7VCC 0.3VCC
AI02791
0.2VCC
Table 10. Capacitance
Symbol COUT CIN Parameter Output Capacitance Input Capacitance Test Condition VOUT = 0V VIN = 0V Min Max 5 5 Unit pF pF
Note: Sampled only, not 100% tested, at TA=25C and a frequency of 1 MHz.
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Table 11. DC Characteristics (M93Sx6, Device Grade 6)
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Test Condition 0V VIN VCC 0V VOUT VCC, Q in Hi-Z VCC = 5V, S = VIH, f = 1 MHz, Current Product 1 ICC Supply Current VCC = 5V, S = VIH, f = 2 MHz, New Product 2 VCC = 5V, S = VSS, C = VSS, Current Product 1 ICC1 Supply Current (Stand-by) VCC = 5V, S = VSS, C = VSS, New Product 2 VIL VIH VOL VOH Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VCC = 5V 10% VCC = 5V 10% VCC = 5V, IOL = 2.1mA VCC = 5V, IOH = -400A 2.4 -0.45 2 15 0.8 VCC + 1 0.4 A V V V V 2 mA Min. Max. 2.5 2.5 1.5 Unit A A mA
50
A
Note: 1. Current product: identified by Process Identification letter F or M. 2. New product: identified by Process Identification letter W or G.
Table 12. DC Characteristics (M93Sx6, Device Grade 3)
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Test Condition 0V VIN VCC 0V VOUT VCC, Q in Hi-Z VCC = 5V, S = VIH, f = 1 MHz, Current Product 1 ICC Supply Current VCC = 5V, S = VIH, f = 2 MHz, New Product 2 VCC = 5V, S = VSS, C = VSS, Current Product 1 ICC1 Supply Current (Stand-by) VCC = 5V, S = VSS, C = VSS, New Product 2 VIL VIH VOL VOH Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VCC = 5V 10% VCC = 5V 10% VCC = 5V, IOL = 2.1mA VCC = 5V, IOH = -400A 2.4 -0.45 2 15 0.8 VCC + 1 0.4 A V V V V 2 mA Min. Max. 2.5 2.5 1.5 Unit A A mA
50
A
Note: 1. Current product: identified by Process Identification letter F or M. 2. New product: identified by Process Identification letter W or G.
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Table 13. DC Characteristics (M93Sx6-W, Device Grade 6)
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Test Condition 0V VIN VCC 0V VOUT VCC, Q in Hi-Z VCC = 5V, S = VIH, f = 1 MHz, Current Product 1 VCC = 2.5V, S = VIH, f = 1 MHz, Current ICC Supply Current (CMOS Inputs) Product 1 VCC = 5V, S = VIH, f = 2 MHz, New Product 2 VCC = 2.5V, S = VIH, f = 2 MHz, New Product 2 VCC = 2.5V, S = VSS, C = VSS, Current Product 1 ICC1 Supply Current (Stand-by) VCC = 2.5V, S = VSS, C = VSS, New Product 2 VIL VIH VOL Input Low Voltage (D, C, S) Input High Voltage (D, C, S) VCC = 5V, IOL = 2.1mA Output Low Voltage (Q) VCC = 2.5V, IOL = 100A VCC = 5V, IOH = -400A VOH Output High Voltage (Q) VCC = 2.5V, IOH = -100A VCC-0.2 V 2.4 0.2 V V -0.45 0.7 VCC 5 0.2 VCC VCC + 1 0.4 A V V V Min. Max. 2.5 2.5 1.5 Unit A A mA
1
mA
2
mA
1
mA
10
A
Note: 1. Current product: identified by Process Identification letter F or M. 2. New product: identified by Process Identification letter W or G.
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Table 14. DC Characteristics (M93Sx6-W, Device Grade 3)
Symbol ILI ILO ICC ICC1 VIL VIH VOL Parameter Input Leakage Current Output Leakage Current Supply Current (CMOS Inputs) Supply Current (Stand-by) Input Low Voltage (D, C, S) Input High Voltage (D, C, S) VCC = 5V, IOL = 2.1mA Output Low Voltage (Q) VCC = 2.5V, IOL = 100A VCC = 5V, IOH = -400A VOH Output High Voltage (Q) VCC = 2.5V, IOH = -100A VCC-0.2 V 2.4 0.2 V V Test Condition 0V VIN VCC 0V VOUT VCC, Q in Hi-Z VCC = 5V, S = VIH, f = 2 MHz VCC = 2.5V, S = VIH, f = 2 MHz VCC = 2.5V, S = VSS, C = VSS -0.45 0.7 VCC Min 1. Max. 1 2.5 2.5 2 1 5 0.2 VCC VCC + 1 0.4 Unit A A mA mA A V V V
Note: 1. New product: identified by Process Identification letter W or G.
Table 15. DC Characteristics (M93Sx6-R)
Symbol ILI ILO ICC ICC1 VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current (CMOS Inputs) Supply Current (Stand-by) Input Low Voltage (D, C, S) Input High Voltage (D, C, S) Output Low Voltage (Q) Output High Voltage (Q) VCC = 1.8V, IOL = 100A VCC = 1.8V, IOH = -100A VCC-0.2 Test Condition 0V VIN VCC 0V VOUT VCC, Q in Hi-Z VCC = 5V, S = VIH, f = 2 MHz VCC = 1.8V, S = VIH, f = 1 MHz VCC = 1.8V, S = VSS, C = VSS -0.45 0.8 VCC Min. 1 Max. 1 2.5 2.5 2 1 2 0.2 VCC VCC + 1 0.2 Unit A A mA mA A V V V V
Note: 1. Preliminary Data: this product is under development. For more infomation, please contact your nearest ST sales office.
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Table 16. AC Characteristics (M93Sx6, Device Grade 6 or 3)
Test conditions specified in Table 8. and Table 5. Symbol fC tPRVCH tWVCH tCLPRX tSLWX tSLCH Alt. fSK tPRES tPES tPREH tPEH Parameter Clock Frequency Protect Enable Valid to Clock High Write Enable Valid to Clock High Clock Low to Protect Enable Transition Chip Select Low to Write Enable Transition Chip Select Low to Clock High Chip Select Set-up Time M93C46, M93C56, M93C66 Chip Select Set-up time M93C76, M93C86 Chip Select Low to Chip Select High Clock High Time Clock Low Time Data In Set-up Time Data In Hold Time Clock Set-up Time (relative to S) Chip Select Hold Time Chip Select to Ready/Busy Status Chip Select Low to Output Hi-Z Delay to Output Low Delay to Output Valid Erase/Write Cycle time Min.3 D.C. 50 50 0 250 250 50 100 250 250 250 100 100 100 0 400 200 400 400 10 Max.3 1 Min.4 D.C. 50 50 0 250 50 50 50 200 200 200 50 50 50 0 200 100 200 200 5 Max.4 2 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
tSHCH
tCSS
tSLSH2 tCHCL1 tCLCH1 tDVCH tCHDX tCLSH tCLSL tSHQV tSLQZ tCHQL tCHQV tW
Note: 1. 2. 3. 4.
tCS tSKH tSKL tDIS tDIH tSKS tCSH tSV tDF tPD0 tPD1 tWP
tCHCL + tCLCH 1 / fC. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles. Current product: identified by Process Identification letter F or M. New product: identified by Process Identification letter W or G.
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Table 17. AC Characteristics (M93Sx6-W, Device Grade 6)
Test conditions specified in Table 9. and Table 6. Symbol fC tPRVCH tWVCH tCLPRX tSLWX tSLCH tSHCH tSLSH2 tCHCL1 tCLCH1 tDVCH tCHDX tCLSH tCLSL tSHQV tSLQZ tCHQL tCHQV tW
Note: 1. 2. 3. 4.
Alt. fSK tPRES tPES tPREH tPEH
Parameter Clock Frequency Protect Enable Valid to Clock High Write Enable Valid to Clock High Clock Low to Protect Enable Transition Chip Select Low to Write Enable Transition Chip Select Low to Clock High
Min.3 D.C. 50 50 0 250 250 100 1000 350 250 100 100 100 0
Max.3 1
Min.4 D.C. 50 50 0 250 50 50 200 200 200 50 50 50 0
Max.4 2
Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns
tCSS tCS tSKH tSKL tDIS tDIH tSKS tCSH tSV tDF tPD0 tPD1 tWP
Chip Select Set-up Time Chip Select Low to Chip Select High Clock High Time Clock Low Time Data In Set-up Time Data In Hold Time Clock Set-up Time (relative to S) Chip Select Hold Time Chip Select to Ready/Busy Status Chip Select Low to Output Hi-Z Delay to Output Low Delay to Output Valid Erase/Write Cycle time
400 200 400 400 10
200 100 200 200 5
ns ns ns ns ms
tCHCL + tCLCH 1 / fC. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles. Current product: identified by Process Identification letter F or M. New product: identified by Process Identification letter W or G.
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Table 18. AC Characteristics (M93Sx6-W, Device Grade 3)
Test conditions specified in Table 9. and Table 6. Symbol fC tPRVCH tWVCH tCLPRX tSLWX tSLCH tSHCH tSLSH2 tCHCL1 tCLCH1 tDVCH tCHDX tCLSH tCLSL tSHQV tSLQZ tCHQL tCHQV tW tCSS tCS tSKH tSKL tDIS tDIH tSKS tCSH tSV tDF tPD0 tPD1 tWP Alt. fSK tPRES tPES tPREH tPEH Clock Frequency Protect Enable Valid to Clock High Write Enable Valid to Clock High Clock Low to Protect Enable Transition Chip Select Low to Write Enable Transition Chip Select Low to Clock High Chip Select Set-up Time Chip Select Low to Chip Select High Clock High Time Clock Low Time Data In Set-up Time Data In Hold Time Clock Set-up Time (relative to S) Chip Select Hold Time Chip Select to Ready/Busy Status Chip Select Low to Output Hi-Z Delay to Output Low Delay to Output Valid Erase/Write Cycle time Parameter Min.3 D.C. 50 50 0 250 50 50 200 200 200 50 50 50 0 200 100 200 200 5 Max.3 2 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Note: 1. tCHCL + tCLCH 1 / fC. 2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles. 3. New product: identified by Process Identification letter W or G.
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Table 19. AC Characteristics (M93Sx6-R)
Test conditions specified in Table 9. and Table 7. Symbol fC tPRVCH tWVCH tCLPRX tSLWX tSLCH tSHCH tSLSH2 tCHCL1 tCLCH1 tDVCH tCHDX tCLSH tCLSL tSHQV tSLQZ tCHQL tCHQV tW tCSS tCS tSKH tSKL tDIS tDIH tSKS tCSH tSV tDF tPD0 tPD1 tWP Alt. fSK tPRES tPES tPREH tPEH Clock Frequency Protect Enable Valid to Clock High Write Enable Valid to Clock High Clock Low to Protect Enable Transition Chip Select Low to Write Enable Transition Chip Select Low to Clock High Chip Select Set-up Time Chip Select Low to Chip Select High Clock High Time Clock Low Time Data In Set-up Time Data In Hold Time Clock Set-up Time (relative to S) Chip Select Hold Time Chip Select to Ready/Busy Status Chip Select Low to Output Hi-Z Delay to Output Low Delay to Output Valid Erase/Write Cycle time Parameter Min.3 D.C. 50 50 0 250 250 50 250 250 250 100 100 100 0 400 200 400 400 10 Max.3 1 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Note: 1. tCHCL + tCLCH 1 / fC. 2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles. 3. Preliminary Data: this product is under development. For more infomation, please contact your nearest ST sales office.
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Figure 10. Synchronous Timing (Start and Op-Code Input)
PRE tPRVCH W tWVCH C tCLSH S tDVCH D START OP CODE tCHDX OP CODE tSHCH tCLCH tCHCL
OP CODE INPUT START
AI02025
Figure 11. Synchronous Timing (Read or Write)
C tCLSL S tDVCH D An tCHQL Q15 tCHDX A0 tSLQZ Q0 tCHQV tSLSH
Hi-Z Q
ADDRESS INPUT
DATA OUTPUT
AI002026
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M93S66, M93S56, M93S46
Figure 12. Synchronous Timing (Read or Write)
PRE tCLPRX W tSLWX C tSLCH tCLSL S tSLSH tDVCH D An tCHDX A0/D0 tSHQV Hi-Z Q BUSY tW ADDRESS/DATA INPUT WRITE CYCLE
AI02027
tSLQZ READY
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PACKAGE MECHANICAL
Figure 13. PDIP8 - 8 pin Plastic DIP, 0.25mm lead frame, Package Outline
b2 A2 A1 b e A L
E
c eA eB
D
8
E1
1 PDIP-B
Note: Drawing is not to scale.
Table 20. PDIP8 - 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
mm Symb. Typ. A A1 A2 b b2 c D E E1 e eA eB L 3.30 2.92 3.30 0.46 1.52 0.25 9.27 7.87 6.35 2.54 7.62 0.38 2.92 0.36 1.14 0.20 9.02 7.62 6.10 - - 4.95 0.56 1.78 0.36 10.16 8.26 7.11 - - 10.92 3.81 0.130 0.115 0.130 0.018 0.060 0.010 0.365 0.310 0.250 0.100 0.300 Min. Max. 5.33 0.015 0.115 0.014 0.045 0.008 0.355 0.300 0.240 - - 0.195 0.022 0.070 0.014 0.400 0.325 0.280 - - 0.430 0.150 Typ. Min. Max. 0.210 inches
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M93S66, M93S56, M93S46
Figure 14. SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, Package Outline
h x 45 A C B e D CP
N
E
1
H A1 L
SO-a
Note: Drawing is not to scale.
Table 21. SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
mm Symb. Typ. A A1 B C D E e H h L 1.27 Min. 1.35 0.10 0.33 0.19 4.80 3.80 - 5.80 0.25 0.40 0 8 0.10 Max. 1.75 0.25 0.51 0.25 5.00 4.00 - 6.20 0.50 0.90 8 0.050 Typ. Min. 0.053 0.004 0.013 0.007 0.189 0.150 - 0.228 0.010 0.016 0 8 0.004 Max. 0.069 0.010 0.020 0.010 0.197 0.157 - 0.244 0.020 0.035 8 inches
N CP
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Figure 15. TSSOP8 3x3mm - 8 lead Thin Shrink Small Outline, 3x3mm body size, Package Outline
D
8
5 E1 E
c
1
4
A1 A CP b e A2
L L1
TSSOP8BM
Note: Drawing is not to scale.
Table 22. TSSOP8 3x3mm - 8 lead Thin Shrink Small Outline, 3x3mm body size, Mechanical Data
mm Symbol Typ. A A1 A2 b c D E E1 e CP L L1 0.550 0.950 0 6 0.400 3.000 4.900 3.000 0.650 0.850 0.050 0.750 0.250 0.130 2.900 4.650 2.900 - Min. Max. 1.100 0.150 0.950 0.400 0.230 3.100 5.150 3.100 - 0.100 0.700 0.0217 0.0374 0 6 0.0157 0.1181 0.1929 0.1181 0.0256 0.0335 0.0020 0.0295 0.0098 0.0051 0.1142 0.1831 0.1142 - Typ. Min. Max. 0.0433 0.0059 0.0374 0.0157 0.0091 0.1220 0.2028 0.1220 - 0.0039 0.0276 inches
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Figure 16. TSSOP8 - 8 lead Thin Shrink Small Outline, Package Outline
D
8
5
c
E1 E
1
4
A1 A CP b e A2
L L1
TSSOP8AM
Note: Drawing is not to scale.
Table 23. TSSOP8 - 8 lead Thin Shrink Small Outline, Package Mechanical Data
mm Symbol Typ. A A1 A2 b c CP D e E E1 L L1 3.000 0.650 6.400 4.400 0.600 1.000 0 8 2.900 - 6.200 4.300 0.450 1.000 0.050 0.800 0.190 0.090 Min. Max. 1.200 0.150 1.050 0.300 0.200 0.100 3.100 - 6.600 4.500 0.750 0.1181 0.0256 0.2520 0.1732 0.0236 0.0394 0 8 0.1142 - 0.2441 0.1693 0.0177 0.0394 0.0020 0.0315 0.0075 0.0035 Typ. Min. Max. 0.0472 0.0059 0.0413 0.0118 0.0079 0.0039 0.1220 - 0.2598 0.1772 0.0295 inches
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M93S66, M93S56, M93S46
PART NUMBERING
Table 24. Ordering Information Scheme
Example: Device Type M93 = MICROWIRE serial access EEPROM (x16) with Block Protection Device Function 66 = 4 Kbit (256 x 16) 56 = 2 Kbit (128 x 16) 46 = 1 Kbit (64 x 16) Operating Voltage blank = VCC = 4.5 to 5.5V W = VCC = 2.5 to 5.5V R = VCC = 1.8 to 5.5V Package BN = PDIP8 MN = SO8 (150 mil width) DW = TSSOP8 (169 mil width) DS2 = TSSOP8 (3x3mm body size) Device Grade 6 = Industrial: device tested with standard test flow over -40 to 85 C 3 = Automotive: device tested with High Reliability Certified Flow 1 over -40 to 125 C Option blank = Standard Packing T = Tape & Reel Packing Plating Technology blank = Standard SnPb plating P = Lead-Free and RoHS compliant G = Lead-Free, RoHS compliant, Sb2O3-free and TBBA-free
Note: 1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy. 2. Available only on new products: identified by the Process Identification letter W or G.
M93S66
-
W MN
6
T
P
Devices are shipped from the factory with the memory content set at all 1s (FFh).
For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office.
Table 25. How to Identify Current and New Products by the Process Identification Letter
Markings on Current Products1 M93S46W6 AYWWF (or AYWWM) Markings on New Products1 M93S46W6 AYWWW (or AYWWG)
Note: 1. This example comes from the S08 package. Other packages have similar information. For further information, please ask your ST Sales Office for Process Change Notice PCN MPG/EE/0059 (PCEE0059).
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REVISION HISTORY
Table 26. Document Revision History
Date Rev. Description of Revision Document reformatted, and reworded, using the new template. Temperature range 1 removed. TSSOP8 (3x3mm) package added. New products, identified by the process letter W, added, with fc(max) increased to 1MHz for -R voltage range, and to 2MHz for all other ranges (and corresponding parameters adjusted). Value of standby current (max) corrected in DC characteristics tables for -W and -R ranges VOUT and VIN separated from VIO in the Absolute Maximum Ratings table Values corrected in AC characteristics tables for -W range (tSLSH, tDVCH, tCLSL) for devices with Process Identification Letter W. Standby current corrected for -R range. Four missing parameters restored to all AC Characteristics tables Table of contents, and Pb-free options added. VIL(min) improved to -0.45V. Absolute Maximum Ratings for VIO(min) and VCC(min) changed. Soldering temperature information clarified for RoHS compliant devices. Device Grade 3 clarified, with reference to HRCF and automotive environments. Process identification letter "G" information added
07-Mar-2002
2.0
26-Mar-2003 14-Apr-2003 23-May-2003 24-Nov-2003 19-Apr-2004
2.1 2.2 2.3 3.0 4.0
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M93S66, M93S56, M93S46
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